Basic Information

• Name in Full: Min-Soo Kim

• Current Mailing Address: 9435 Dogwood Garth LN, Mechanicsville, VA 23116, USA

• E-mail Address: jikjian@gmail.com

• Contact Number: Tel: +1 (804) 550 7779 (Home), +1-804-484-2265 (Cell)

Objective & Background

I have been in the DRAM silicon industry for more than fourteen years with proven technical skills and knowledge, problem solving skills, project management skills, and leadership to lead cross-functional teams while mentoring colleagues. I want to continue professional career in the silicon industry or related industry as a FEOL Process Integration Engineer or a Technical Project Manager and expand knowledge in semiconductor or related industry and contribute the greater good for the society.

Summary of Qualification

• Excellent understanding of MOS-C, MOSFET, CMOS device.
• Excellent understanding of DRAM/SRAM/Flash cell operations.
• Excellent verbal and written communication skills.
• Very good understanding on hardware configuration and concept for cleaning, deposition, and etch.

• Understand both R&D and volume Manufacturing environment, and Technology Transfer process.

• Detail oriented, dedicated, self-motivated, goal oriented, and very timeline cautious.
• Critical thinker, Fast Learner, Doer, Leader.
• Native speaker of Korean, proficient English speaking, Comprehension of Chinese characters.
• Hands on experiences on;

  • APCVD, LPCVD, ALD, I-V, C-V characterization, high k dielectrics, Project Management, PROMIS, VAX, FAB300, FreeBSD, Windows, PowerPoint, Excel, MS Word, MySQL, Web Application, Origin, JMP, RS1, RPL, DoE, SPC, Lean 6 Sigma, C/C++, Perl, PHP, HTML, Wiki.

Professional Work Experience & Research Activities

Jul 2002 ~ Feb 2009: Technology Transfer, Process Integration, Qimonda North America

Staff Engineer

Worked in 300mm factory as part of DT(Deep Trench) Capacitor Module Process Integration of 70nm technology and coordinating transfer of new process and product into mass production site and ensuring rapid yield learning and ramping.

Key member of 110nm technology transfer and rapid yield ramp up for the 200mm factory since 2002. Resolved various yield loss issues by leading cross-functional activities.

Worked as a 300mm factory start-up member in 2004 and played key role for the very successful 1st Si for the 110nm technology transfer. Ever since, have been a key member of 300mm factory optimization and almost all technology transfer into 300mm factory. Developed robust doped poly process to resolve trench node leakage issue to improve yield by more than 30%, and have been conducting multiple cross-functional task force teams to resolve various yield loss issues. While working on 90nm yield project, included bevel, wafer edge, and backside process characterization as part of silicon processing and demonstrated optimization of bevel, wafer edge, and backside integrity plays critical role for the yield improvement and ensuring line stability.

Sep.2001 ~ Jun. 2002: DRAM Development Alliances, Infineon Technologies Corporations.

Senior Engineer

Worked as part of process integration of 110nm vertical transistor technology. Despite the short duration of the work in DDA, successfully completed three major tasks for Deep Trench DRAM technology. Firstly, developed robust node nitride process to enable to achieve higher node capacitance while ensuring long term node reliability by optimizing surface treatment. Secondly, developed reliable surface enhancement technology using HSG(Hemispherical Silicon Grains) that overcomes the demanding high aspect ratio of Deep Trench technology by optimizing gas, pressure, and time settings through extensive DoEs. Thirdly, developed mass production worthy wet bottle process by optimizing number of Si etching cycles and optimizing Modified Anti-Collar process. Furthermore, to overcome demanding aspect ratio of Deep Trench technology for poly to fill, worked with poly refill process and divot-fill process to make better doped poly filling process to ensure lower resistivity conducting wire within the trench.

Nov.1999 ~ Aug. 2001: Diffusion, Ichon Manufacturing Division, Hyundai Electronics Industries, Co., Ltd.

Manager

Managed mass production of 250nm FLASH / SRAM / DRAM devices and their yield analysis and yield improvement project. Perform biweekly analysis of in-line data by RS/1 and provide accurate and timely yield reports. Also provided web based intranet for knowledge accumulation and collaboration..

As a diffusion manager, involved on the wafer quality monitoring to ensure full product quality. Worked with wafer vendors to constantly monitor basic silicon substrate quality. Obtained in-depth knowledge of wafer substrate quality and manufacturing procedure and its impact on final product. Conducted wafer vendor-to-vendor quality comparison as well as factory-to-factory fully final product quality comparisons.

Apr.1999 ~ Oct.1999: Cap Module, Semiconductor R&D Center, Hyundai Electronics Industries, Co., Ltd.

Senior Engineer

Involved in the “Development of ALD(atomic-layer deposition) process for sub-150nm Device”. Worked with tool vendor to develop alpha version of ALD tool configuration and concept. Using this alpha version ALD tool, researched the “application of Al2O3 grown by atomic layer deposition to DRAM and FeRAM”. Extensive study on the basic properties of ALD Al2O3 was performed. Showed that metal-insulator-silicon(MIS) Al2O3 capacitor with a HSG cylinder bottom electrode is better than MIS Ta2O5 capacitor. Also, showed that Al2O3 has good properties of hydrogen barrier for SBT capacitor in FeRAM.

Jun.1997 ~ Mar.1999: Cap Module, Semiconductor R&D Center, Hyundai Electronics Industries, Co., Ltd.

Senior Engineer

Involved in the “Development of Next-Generation Capacitor Technology”. Basic issues were covered on the various capacitor dielectric, cylinder structure formation, impact of design rule, and capacitor process integration with self-aligned-contact process. Found the space margin limitation of outer-cylinder structure using E-beam lithography for 130nm design rule. Based on the result, turned the capacitor structure from outer-cylinder to inner-cylinder for 0.18mm devices and beyond. It was considered a big milestone for the stack capacitor technology road map.

Oct.1995 ~ May.1997: Cap Module, Semiconductor R&D Center, Hyundai Electronics Industries, Co., Ltd.

Senior Engineer

Involved in the “Development of 180nm Capacitor Technology using selective HSG and N/O dielectric for 1G bit SDRAM”. Basic properties of the selective HSG process were researched by using various machines including Anelva UHV system, ASM A600 system and JEL Eureka system. Found the optimum condition for the selective HSG process by conducting very sophisticated DoEs. Sufficient capacitance for device operation was achieved by using selective HSG with area-enlargement-factor(AEF) of about 2.0 on a cylinder structure.

Jan.1995 ~ Sep.1995: Cap Module, Semiconductor R&D Center, Hyundai Electronics Industries, Co., Ltd.

Junior Engineer

Involved in the “Development of 250nm Capacitor Technology using conventional HSG and N/O dielectric for 256M bit SDRAM”. Optimized the conventional (deposited) HSG to have AEF of about 1.5~1.7 on a cylinder structure. Also, lowered the Tox(equivalent oxide thickness) limit of N/O dielectric to 43Å using surface treatment prior to Si3N4 deposition and post-deposition surface treatment.

Education

Jan.1992 ~ Feb.1995: Department of Physics, Sogang University, Seoul, 121-742 KOREA.

• Graduate Student, Master of Physics.
  • Basic studies on the properties of bulk ferro-electric material were performed. One of the most interesting problems in ferro-electric, perovskite oxide material is that of “polarization reversal”. My M.S thesis, “The Influence of KDP Doping on the Polarization Reversal of TGS”, explained how dislocation or defect density affects the properties of switching characteristics of polarization reversal by domain wall motion theory and nucleation model. During this period of time, basic of CZ crystal growth, sintering of ceramics, fuzzy PID temperature control, hysteresis curve and C-V, I-V measurement, unit operation, and building hardware interface using C language were the scope of the study.

Publication & Patent

Journal Papers (not including 11 internal technical note written in Hynix[Hyundai Electronics])

1. Min-Soo Kim, Chan Lim, Young-Jin Park, and Jong-Cheol Kim, “Resistivity Behavior of in-situ Doped Poly-silicon with Annealing Temperature”, The Korean Material Research Society, Spring (1996).

2. Min-Soo Kim, Kyoung-Min Kim, Kiseon Park, Chan Lim, “Production-Worthy Full Process Integration of Ta2O5 Capacitor Technology”, International Workshop on Advanced LSI’s and Devices (1999).

3. C.T. Kim, C.Lim, K.M Kim, M.S. Kim, H.L, Jang, Y.S. Yu and J.S. Rho, “Application of Al2O3 Grown by Atomic Layer Deposition to DRAM and FeRAM”, 12th International Symposium on Integrated Ferroelectrics, Spring (2000).

4. H.Akatsu, R.Weis, K.Cheng, M.Seitz, M-S.Kim, R.Ramachandran, T.Dyer, B.Kim, et al, “A Highly Manufacturable 110nm DRAM Technology with 8F2 Vertical Transistor Cell for 1Gb and Beyond”,VLSI Technology Digest of Technical Papers 2002 Symposium, (2002).

5. Fen Chen, Porshia Parkinson, Irene McStay, Kenneth Settlemyer, Robert Revieere, Helmut Tews, Mihel Seitz, Min-Soo Kim, Michael Ruprecht, Jinghong Li, Rajarao Jammy, Alvin Strong, “Time-dependent dielectric Breakdown Evaluation of Deep Trench Capacitor with Sidewall Hemispheical, Polysilicon Grains for Gigabit DRAM Technology”, Integrated Reliability Workshop (2002).

6. Min-Soo Kim, Willian Cooper, Brian Simonson, David Ricks, Eric McDaniel, Roderick Miller, Richard Chapman, Thomas Taylor, Robert Fuller, “Deep Trench Resistance and Leakage Reduction – poly1 doping process optimization in high volume DRAM Manufacturing for 300mm factory”, Advanced Semiconductor Manufacturing Conference (2006)

Patents (not including 19 Korean patents)

1. Min-Soo Kim, Chan Lim, “Method for manufacturing a semiconductor device having incorporated therein a high k capacitor dielectric”, US6486021, 2000.

2. Min-Soo Kim, Kyong-Min Kim, Chan Lim, Heung-Sik Kwak, Chung-Tae Kim, “Method for manufacturing aluminum oxide film for use in a semiconductor device “, US6589886, 2000.

3. Min-Soo Kim, Lim Chan, “Semiconductor device incorporated therein high k capacitor dielectric and method for the manufacture thereof”, US6633062, 2002.

4. Oh-Jung Kwon, Kenneth T. Settlemyer, Jr., Ravikumar Ramachandran, Min-Soo Kim, “Method of fabricating a bottle trench and a bottle trench capacitor”, US7122439, 2004.

5. Min-Soo Kim, Jonathan Davis, Debra Heier Arnold, Robert Fuller, “Recessed collar etch for buried strap window formation without poly2”, Pending, 2005.

References